1. Field of the Invention
The present disclosure generally relates to telecommunication techniques and has been developed with particular but not exclusive attention paid to its possible application to telecommunication systems based upon the CDMA/3GPP FDD standard (where said acronyms stand for Code-Division Multiple Access/Third-Generation Partnership Project Frequency Division Duplex).
Even if in what follows, for reasons of clarity and simplicity of exposition, practically exclusive reference will be made to this application, it should, however, borne in mind that the scope of the invention is more general. The invention is, in fact, applicable to all the telecommunication systems in which operating conditions of the type described in what follows occur: by way of non-exhaustive example, the satellite-telecommunication systems and the mobile cellular systems corresponding to the UMTS, CDMA2000, IS95 or WBCDMA standards may be cited.
2. Description of the Related Art
To enable acquisition of a base station by a mobile terminal included in a telecommunication system based upon the standard 3GPP FDD mode or the like, the corresponding receiver requires means capable of carrying out the function of frame synchronization and identification of the so-called codegroup. The possibility of executing the said functions is essential for the execution of the subsequent steps in the context of the cell-search system.
In particular, when a mobile terminal is turned on, it does not have any knowledge of the timing of the transmitting cell to which it is to be assigned. The 3GPP standard, therefore, proposes an initial cell-search procedure for acquiring the cell signal and synchronizing therewith.
Said procedure basically comprises three steps:                slot synchronization (first step);        frame synchronization and identification of the codegroup, i.e., the group of cell codes (second step); and        identification of the scrambling code (third step).        
In the implementation of the second step described above, it is assumed that the slot synchronization has previously been obtained during the first step.
To obtain at this point the frame synchronization and identify the codegroup, in the second step the Secondary Synchronization Channel (SSCH) is used, on which there are transmitted, at the beginning of each slot, 256-chip codes (i.e., letters).
The sixteen 256-chip complex codes used by the standard are generated on the basis of the following rules:                a first sequence at chip rate b having a repetition period of 16 (i.e., repeating every 16 elements) is multiplied by a sequence 16 times slower according to the two formulas appearing below so as to obtain the base sequence z:z=<b, b, b, −b, b, b, −b, −b, b, −b, b, −b, −b, −b, −b, −b>b=<1, 1, 1, 1, 1, 1, −1, −1, −1, 1, −1, 1, −1, 1, 1, −1>        
The base sequence z is then multiplied element by element by a Hadamard code of length 256 chosen according to the following rule: if m is the number identifying the Secondary Synchronization Code (SSC) to be generated, the number of the Hadamard code to be multiplied by the sequence z is equal to 16×(m−1), with m ranging from 1 to 16.
In the solutions known to the art, execution of the second step of cell search envisages that in a frame there will be transmitted on the Synchronization CHannel (SCH) only 15 Secondary Synchronization Codes SSCs making up a word which identifies the cell. The possible letters are sixteen (as many as the codes). Of all the possible words made up of 15 letters that can be formed from the previous set (formed by the 16 letters), the standard uses only a set of 64 possible words (belonging to a Reed-Solomon code defined by the standard).
To identify a single letter, the solutions according to the known art envisage sending the input to a bank of correlators or to a bank of furniture which carry out the Fast Hadamard Transform (FHT), so as to obtain at output the energies corresponding to the individual letters.
The values representing the energy of the individual letters (codes) are appropriately summed and stored in a bank of registers, in which each row represents one of the words of the code that is to be recognized. The columns represent, instead, the possible starting points of the frame in the slot (15 possible starting points).
The above solution is schematically represented in the diagram of FIG. 1, where the reference 10 designates a bank of correlators at the output of which signals indicating the energies of the individual letters are generated. After a possible masking, represented by a block 12, the energies are added in a node 14 and are then stored in a bank of registers 16.
In the example represented in FIG. 1, the bank 16 comprises 64 rows and 15 columns, each row representing one of the words of the code that is to be recognized, whilst each of the columns represents a possible starting point of the frame.
Designated by the reference number 18 is a block basically comprising a comparator which enables the search for the maximum value on the memory bank 16 to be carried out, so as to define both the codegroup CD used by the cell currently being evaluated and the start of the frame, basically expressed as frame offset OF, transmitted by the cell itself; it is, in other words, a quantity which identifies the frame synchronization with reference to the slot timing obtained in the first step (not illustrated specifically in the drawings).
The solution according to the known art represented in FIG. 1 requires therefore a memory formed by 64 rows and 15 columns, where each cell is formed by (n+log215) bits, where n corresponds to the number of bits at output from the bank of correlators.
An accumulator is moreover necessary, which adds the energy of the new letter for the word corresponding to the memory cell according to the value contained therein. This is performed for all the 64*15 memory cells, with an appropriate choice of the letters to be added each time. Said choice is managed by a control unit 20 programmed with an appropriate software.